
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 9
100 Freescale Semiconductor
Figure 73. Boundary Scan (JTAG) Timing Diagram
Figure 74. Test Access Port Timing Diagram
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
Data
Outputs
VIH
VIL
Input Data Valid
Output Data Valid
Output Data Valid
SJ4
SJ5
SJ6
SJ7
SJ6
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
TDO
(Output)
VIH
VIL
Input Data Valid
Output Data Valid
Output Data Valid
TMS
SJ8 SJ9
SJ10
SJ11
SJ10
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