
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 9
68 Freescale Semiconductor
NOTE
For timing purposes, transition to signal high is defined as 80% of signal
value; while signal low is defined as 20% of signal value.
Timing for HCLK is 133 MHz. The internal NFC clock (Flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not related to the NFC clock.
3.7.6.3 Wireless External Interface Module (WEIM) Timing
Figure 38 depicts the timing of the WEIM module, and Table 56 describes the timing parameters
(WE1–WE27) shown in the figure.
All WEIM output control signals may be asserted and negated by internal clock relative to BCLK rising
edge or falling edge according to corresponding assertion/negation control fields. Address always begins
relative to BCLK falling edge, but may be ended on rising or falling edge in muxed mode according to the
control register configuration. Output data begins relative to BCLK rising edge except in muxed mode,
where rising or falling edge may be used according to the control register configuration. Input data, ECB
and DTACK are all captured relative to BCLK rising edge.
NF5 NF_WP pulse width tWP T–1.5 ns 28.5 ns
NF6 NFALE setup time tALS T — 30 — ns
NF7 NFALE hold time tALH T–3.0 ns — 27 — ns
NF8 Data setup time tDS 2T ns — 60 — ns
NF9 Data hold time tDH T–5.0 ns — 25 — ns
NF10 Write cycle time tWC 2T 60 ns
NF11 NFWE
hold time tWH T–2.5 ns 27.5 ns
NF12 Ready to NFRE
low tRR 21T–10 ns — 620 — ns
NF13 NFRE
pulse width tRP 1.5T — 45 — ns
NF14 READ cycle time tRC 2T — 60 — ns
NF15 NFRE
high hold time tREH 0.5T–2.5 ns 12.5 — ns
NF16 Data setup on read tDSR N/A 10 — ns
NF17 Data hold on read tDHR N/A 0 — ns
1
The Flash clock maximum frequency is 50 MHz.
Table 55. NFC Timing Parameters
1
(continued)
ID Parameter Symbol
Timing
T = NFC Clock Cycle
Example Timing for
NFC Clock
≈ 33 MHz
T = 30 ns
Unit
Min. Max. Min. Max.
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